As electronic circuits have become increasingly complex and miniaturized, they have also become more difficult to test. Among the various techniques that are used to test them is the “Standard Test Access Port and Boundary Scan Architecture” (IEEE 1149.1). This standard provides a way to read and to change the state of input and output (I/O) pins on an integrated circuit. The standard was developed by the Joint Test Action Group (JTAG), so the interface added to an integrated circuit to provide test access to the input and output pins is often called a JTAG interface. Signals between the core logic of the integrated circuit and the I/O pins on the integrated circuit that are to be accessed by the JTAG interface pass through a boundary scan register, with at least one cell in the boundary scan register for each I/O pin to be accessed. During normal operation, signals are passed through the boundary scan register without change. In a test mode, either the I/O pins or the core logic of the integrated circuit may be disconnected at the boundary scan register, allowing the JTAG interface to read and write values in the boundary scan register and thus to the devices that remain connected to the boundary scan register, whether the I/O pins or the core logic of the integrated circuit. The JTAG interface adds four or five pins to the interface of the integrated circuit, so that a testing device connected with the JTAG interface can read and write the values in the boundary scan register and other registers such as an instruction register and data registers. The JTAG interface is a serial interface that shifts values in and out of the boundary scan register or other registers one bit at a time, under the control of a Test Access Port (TAP) controller.
Often, multiple devices in an electronic circuit include JTAG interfaces allowing each device to be tested. This may be accomplished in conventional systems by providing a separate JTAG interface for each device, requiring separate JTAG pins to be added to each device. This may also be accomplished in conventional systems by providing a single set of JTAG pins in the electronic circuit and daisy chaining multiple TAP controllers together from the single set of JTAG pins. Although this method does allow multiple JTAG interfaces to share a single set of JTAG pins, it requires that instructions written to the daisy chained TAP controllers be concatenated and that data read from the daisy chained TAP controllers be divided to separate the concatenated data.